In a large-scale integrated circuit (LSI), a large number of logic circuits are used. The logic circuits are roughly classified into logic gates and bistable logic circuits. The logic gate is used to process a digital logic value, and represented by an inverter, an NAND gate, or an NOR gate. The bistable logic circuit is used to temporarily hold or store a digital logic value, and represented by any of various types of latch circuits, or any of various types of flip-flop circuits combining them. A typical LSI incorporates large numbers of logic gates and bistable logic circuits, which are combined with each other. In recent years, the LSI often simultaneously incorporates a memory core such as a random access memory (RAM) or a read only memory (ROM).
In the recent LSI, due to development of miniaturization technique in a manufacturing process, a huge number of logic circuits have been integrated. Along with this, an increase in operating power due to an increase in speed, and an increase in standby power represented by a leak current become problems. As one of solutions of the problems, there is known a method that stops supplying power to an unused circuit block or to an entire LSI. However, this method causes an initial data, intermediate process data, result data, or the like to disappear. For this reason, a procedure for, immediately before the stop of the power supply, transferring the processing data to a nonvolatile storage device is required. This causes power supply control to be complicated, and a component cost in a system to be increased. Also, at the time of a power failure due to lightening, or an instantaneous power failure due to an unforeseen accident or the like, the procedure for transferring the processing data may not be appropriately performed. Further, in a latch circuit or a flip-flop circuit, an initial data is arbitrary, and therefore an initializing operation of a logic circuit is required at the time of power-on, which is disadvantageous in that system activation is delayed.
As means adapted to solve the above-described problems, there is proposed a circuit innovation that can hold a state of the latch circuit or the flip-flop circuit even after the stop of the power supply. For example, Japanese Patent Publication No. JP-A-Heisei 5-218850 (corresponding to U.S. Pat. No. 5,486,774A) proposes a flip-flop circuit that uses a virtual power supply through a power supply switch. Upon operation, the flip-flop circuit brings the power supply switch into an ON state, and operates with both of a main power supply and the virtual power supply to keep high-speed performance. Upon standby, the power supply switch is brought into an OFF state, and the virtual power supply is interrupted to hold a state of the flip-flop circuit only with the main power supply. This enables a reduction in power to be expected.
As a means adapted to solve the above-described problems, there is also proposed a method that combines a flip-flop circuit and a nonvolatile memory element. For example, Japanese Patent Publication No. JP2004-88469A (corresponding to U.S. Pat. No. 7,080,270B2) proposes a circuit that stores a state of a flip-flop circuit in a ferroelectric capacitor. In the circuit, an output of an inverter used for the flip-flop circuit is connected with the ferroelectric capacitor, and it is not necessary to separately provide a writing means. For example, Japanese Translation of PCT No. 2002-511631 (corresponding to European Patent Publication No. EP1,072,040A1), Japanese Patent Publication No. JP2003-157671A, or Japanese Patent Publication No. JP2004-206835A (corresponding to US Patent Publication No. US2004/125660A1) proposes a circuit that stores a state of a latch circuit in a magnetoresistance element (e.g.: MTJ element). In the circuit, between an inverter of the latch circuit and a power supply, the MTJ element is inserted, and writing means adapted to store a state of a flip-flop circuit in the MTJ element is provided. It is generally said that the number of rewrites in the MTJ element is infinite (1015 times or more). Accordingly, the circuit can constantly perform the store operation. Also, the writing can be performed as quick as a few nano-seconds or less. Further, the MTJ element is deposited in a wiring line manufacturing process, and therefore can be stacked just above a transistor. Accordingly, an overhead of a cell layout area may be able to be suppressed.
As a related technique, Japanese Patent Publication No. JP2007-207406A (corresponding to US Patent Publication No. US2007/159876A1) discloses a semiconductor memory device. The semiconductor memory device is provided with: a memory cell array including memory cells arranged in a matrix; and a sense amplifier circuit. Each of the memory cells includes at least one magnetoresistance element storing data, and amplifying means adapted to amplify potential generated by current flowing through the magnetoresistance element. The sense amplifier circuit identifies the data stored in the magnetoresistance element in response to output of the amplifying means.
Also, Japanese Translation of PCT No. 2006-526907 (corresponding to US Patent Publication US2007/164781A1) describes a component having a logic circuit device that can configure a function. The component has the logic circuit device capable of configuring the function, and includes a plurality of data lines (7). In the component, at least one part of the data lines (7) is related to at least one element (1) that can switch between two states respectively having different discrete resistances, and the component is characterized in that according to a state switched through the element (1), the data line (7) is opened or interrupted; at the time, a switched state of the element (1) can be stored with being nonvolatile; and the switching can be quickly made.
Further, International Patent Publication No. WO2003/085741 (corresponding to US Patent Publication US2004141363A1) discloses a nonvolatile flip-flop. The nonvolatile flip-flop includes a flip-flop unit having a pair of storage nodes for storing a pair of reverse logic data, and a pair of non-volatile resistance change elements respectively connected to the pair of storage nodes and changing their resistances in such a manner that they can be stored. In the store operation, the resistances of the pair of non-volatile resistance change elements are changed according to potentials of the pair of storage nodes, and in recall operation, each of the pair of storage nodes can be set to a potential corresponding to a difference between the resistances of the pair of non-volatile resistance change elements.
Still further, Japanese Patent Publication No. JP-A-Heisei 8-191234 discloses a D flip-flop circuit. In the D flip-flop circuit, a master includes a first inverter (I1) constituting a feedforward path, a second inverter (I2) constituting a feedback path, and first transfer gate (TG1); a slave includes a third inverter (I3) constituting a feedforward path, a fourth inverter (I4) constituting a feedback path, and a second transfer gate (TG2); a third transfer gate (TG3) is provided between an input terminal of the D flip-flop circuit and the first inverter (I1); a fourth transfer gate (TG4) is provided between the master and the slave; the second and third transfer gates (TG2 and TG3) are controlled by a first control signal (S1); and the first and fourth transfer gates (TG1 and TG4) are controlled by a second control signal (S2) having a phase opposite to that of the first control signal (S1).
The D flip-flop circuit is characterized by including: a fifth transfer gate (TG5) that interrupts the feedback path of the master when the D flip-flop circuit returns from power save; a sixth transfer gate (TG6) that interrupts the feedback path of the slave when the D flip-flop circuit returns from the power save; a positive terminal; and a negative terminal, and having: a storage circuit (M1) that outputs a true value to the positive terminal and a value opposite to the true value to the negative terminal for data written from the positive terminal, and outputs a true value to the negative terminal and a value opposite to the true value to the positive terminal for data written from the negative terminal, wherein the master and the slave are supplied with power supplies different from each other; a seventh transfer gate (TG7) that interrupts a path between a negative terminal of the storage circuit (M1) and an input terminal of the first inverter (I1) when the D flip-flop circuit is in the power save; an eighth transfer gate (TG8) that interrupts a path between a positive terminal of the storage circuit (M1) and an input terminal of the third inverter (I3) when the D flip-flop circuit is in the power save; and a ninth transfer gate (TG9) that interrupts the path between the negative terminal of the storage circuit (M1) and the input terminal of the first inverter (I1) when the master and the slave are interrupted by the second control signal (S2).
Yet further, Japanese Patent Publication No. JP-A-Showa 63-136386 (corresponding to U.S. Pat. No. 4,751,677) describes a multiple magnetic structures memory cell. The multiple magnetic structures memory cell includes: a plurality of storage structures including a first storage structure and a second storage structure; first and second impedance means; and first and second switching means.
In the latch circuit or the flip-clop circuit using a power supply switch and a virtual power supply, a special manufacturing process for a memory element is not required. However, the main power supply is not stopped, and therefore it is necessary to use a transistor having a high threshold voltage to prevent an increase in a gate leak current or a sub-threshold leak current. Also, three power supply lines, i.e., a main power supply line, a virtual power supply line, and ground line, are required, which complicates layout, and therefore it is difficult to make a design with an automatic layout tool. Accordingly, there is a problem of art increase in design cost.
In the latch circuit or the flip-flop circuit using a ferroelectric capacitor, a high temperature process is required to manufacture the ferroelectric capacitor. Accordingly, it is difficult to stack the ferroelectric capacitor on a wiring layer. For this reason, it is necessary to form the ferroelectric capacitor on a semiconductor substrate, which increases a cell area of the flip-flop circuit. Also, upon a store operation, a load capacitance of an inverter used for the flip-flop circuit is increased. Further, a time for writing to the ferroelectric capacitor requires a few tens nano-seconds, and therefore operating speed is reduced. Still further, it is necessary to wire a low impedance plate line to one of terminals of the ferroelectric capacitor, and therefore it may be difficult to make a design with an automatic layout tool.
In the latch circuit or the flip-flop circuit using a magnetoresistance element (e.g.: MTJ element), current flows through a wiring layer positioned below or above the MTJ element, and a magnetization direction of the MTJ element is reversed by a magnetic field generated by the current to perform writing. An efficiency for generating the magnetic field by current flowing is low, and typically a current of a few mA is required. Accordingly, a size of a transistor used for a current supplying means used also for the latch circuit is increased, and an increase in a cell area of the flip-flop is inevitable. Further, a signal amount (a difference between low and high resistive states) of the MTJ element is as small as 100% or less. Upon recall operation, inputs/outputs of inverters cross-coupled to each other are short-circuited to perform reading with a combined resistance of an ON resistance of a transistor and a resistance of the MTJ element, and therefore the signal amount is further reduced. For this reason, considering a variation in a threshold voltage of the transistor and a variation in resistance of the MTJ element, it is not easy to normally perform the recall operation.